(China (Mainland))
Product Summary
The NDS352P/AP is a P-Channel logic level enhancement mode power field effect transistor. The NDS352P/AP is produced using Fairchild’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The NDS352P/AP is particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
Parametrics
NDS352P/AP absolute maximum ratings: (1)Drain-Source Voltage:-20 V; (2)Gate-Source Voltage - Continuous:±12 V; (3)Maximum Drain Current: Continuous:±0.85A, Pulsed:±10A; (4)Maximum Power Dissipation:0.5 W; (5)Operating and Storage Temperature Range:-55 to 150℃.
Features
NDS352P/AP features: (1)-0.85A, -20V. RDS(ON) = 0.5Ω @ VGS = -4.5V; (2)Proprietary package design using copper lead frame for superior thermal and electrical capabilities; (3)High density cell design for extremely low RDS(ON); (4)Exceptional on-resistance and maximum DC current capability; (5)Compact industry standard SOT-23 surface mount package.
Diagrams
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 NDS331N |
Fairchild Semiconductor |
MOSFET N-Ch LL FET Enhancement Mode |
Data Sheet |
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NDS331N_D87Z |
Fairchild Semiconductor |
MOSFET N-Ch LL FET Enhancement Mode |
Data Sheet |
Negotiable |
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NDS331N_Q |
Fairchild Semiconductor |
MOSFET N-Ch LL FET Enhancement Mode |
Data Sheet |
Negotiable |
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NDS332P |
Fairchild Semiconductor |
MOSFET SOT-23 P-CH LOGIC |
Data Sheet |
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NDS332P_D87Z |
Fairchild Semiconductor |
MOSFET P-Ch LL FET Enhancement Mode |
Data Sheet |
Negotiable |
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NDS332P_Q |
Fairchild Semiconductor |
MOSFET SOT-23 P-CH LOGIC |
Data Sheet |
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