(China (Mainland))
Product Summary
The K4D263238I-UC50 is a 134,217,728 bits, hyper synchronous data rate Dynamic RAM organized as 4 × 1,048,576 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 2.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the K4D263238I-UC50 to be useful for a variety of high performance memory system applications.
Parametrics
K4D263238I-UC50 absolute maximum ratings: (1)Voltage on any pin relative to Vss, VIN, VOUT: -0.5 ~ 3.6 V; (2)Voltage on VDD supply relative to Vss, VDD: -1.0 ~ 3.6 V; (3)Voltage on VDD supply relative to Vss, VDDQ: -0.5 ~ 3.6 V; (4)Storage temperature, TSTG: -55 ~ +150℃; (5)Power dissipation, PD: 1.8 W; (6)Short circuit current, IOS: 50 mA.
Features
K4D263238I-UC50 features: (1)Data I/O transactions on both edges of Data strobe ; (2)DLL aligns DQ and DQS transitions with Clock transition; (3)Edge aligned data & data strobe output; (4)Center aligned data & data strobe input ; (5)DM for write masking only; (6)Auto & Self refresh; (7)32ms refresh period (4K cycle); (8)100pin TQFP package; (9)Maximum clock frequency up to 250MHz; (10)Maximum data rate up to 500Mbps/pin; (11)Full page burst length for sequential burst type only; (12)Start address of the full page burst should be even; (13)All inputs except data & DM are sampled at the positive going edge of the system clock; (14)Differential clock input; (15)Write Interrupted by Read function; (16)2.5V ± 5% power supply for device operation; (17)2.5V ± 5% power supply for I/O interface; (18)SSTL_2 compatible inputs/outputs; (19)4 banks operation; (20)MRS cycle with address key programs.
Diagrams
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K4D263238A-GC |
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K4D263238A-GC33 |
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K4D263238E-GC |
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K4D263238E-GC33 |
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