Product Summary

The HD6417750RF200V is a 32-bit RISC microprocessor, featuring object code upward-compatibility with SH-1, SH-2, and SH-3 microcomputers. The HD6417750RF200V includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation lookaside buffer). The HD6417750RF200V has a 16-kbyte instruction cache and a 32-kbyte data cache. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.

Parametrics

HD6417750RF200V absolute maximum ratings: (1)I/O, PLL, RTC, CPG power supply voltage VDDQ: –0.3 to 4.2 V; (2)Internal power supply voltage VDD: –0.3 to 2.5 V; (3)Input voltage Vin: –0.3 to VDDQ + 0.3 V; (4)Operating temperature Topr: –20 to 75 ℃; (5)Storage temperature Tstg: –55 to 125 ℃.

Features

HD6417750RF200V features: (1)Superscalar architecture: Parallel execution of two instructions; (2)Packages: 256-pin BGA, 208-pin QFP, 264-pin CSP; (3)External buses: Separate 26-bit address and 64-bit data buses, External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency; (4)Original Hitachi SH architecture; (5)32-bit internal data bus; (6)Superscalar architecture (providing simultaneous execution of two instructions) including FPU; (7)Instruction execution time: Maximum 2 instructions/cycle; (8)Virtual address space: 4 Gbytes (448-Mbyte external memory space); (9)Space identifier ASIDs: 8 bits, 256 virtual address spaces; (10)On-chip multiplier; (11)Five-stage pipeline.

Diagrams

HD6417750RF200V diagram

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